NHD-C0216CIZ-FSW-FBW-3V3 unexpected I2C levels

kentavv

I'm controlling a NHD-C0216CIZ-FSW-FBW-3V3 from a BeagleBone Black via I2C. The BBB has no pull-up resistors on the I2C lines exposed to the headers. A 1.5K ohm resistor works well on the SCL line and limits the current to below the 3mA maximum. However, any resistor below 50K ohm prevents acknowledgements from the the display from reaching the BBB.

I believe the problem is because of the rather high voltage level that the display uses for a logic low. The attached scope image shows a failed acknowledgement. (Well, the scope serial decoder sees the acknowledgement, but the BBB must sample SDA during the falling edge of SCL.) The low voltage level is nearly 900mV and barely below the maximum allowed by the I2C spec of 0.3 * Vdd = 0.3 * 3.3 = 1.0V. In this particular case, there a spike near the fallowing edge of SCL, and the spike puts the acknowledgement's level at nearly 2V. The ground is solid as are the connection.

I'm starting to think that the display does not implement I2C well. Compare the acknowledgement low from the display vs. the nearly 0 V low from the BBB. The manual for the display suggests 0.4V for the low while the referenced driver, which uses DB6/7 for the I2C lines, and that manual says 0.8V is the expected low level. 0.8V is close to what I'm seeing, but a pretty marginal I2C low when Vdd = 3.3V.

I'm not sure what causes the spikes. I've isolated the SDA lines from the others without any change. However, if the display's logic low was nearer to 0 V, the spikes may not be an issue.

I could be completely misinterpreting the materials here, so any guidance would be greatly appreciated. I'm willing to provide any other information or perform additional tests. In the meantime, I'm going to try a NXP parallel I2C to one of New Haven Display's parallel interface modules and see if that combination works better.

One other small item, the display manuals use wording that can unfortunately be interpreted different ways. Does an ACK from the display indicate the busy flag is no longer busy?

Thank you, Kent

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Comments

3 comments

Date Votes
  • Saurabh_B
    Hello Kent,

    I will need to power this display up to see if I can replicate the spikes being caused by this display.

    Unfortunately the Logic LOW for the ACK is caused by the controller.

    We will have to update this spec to match the output voltage from the controller.
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  • jojahn

    Hi there,
    I just got few displays in the mail. I tested two of them on I2C with different speeds, different pull-up resistors etc. I just can't get the ACK back.
    I wrote a VB6 software and using my serial port to bit bang the traffic. It works fine with I/O Chips.... any idea?
    I have a short "PING" version, where I just call the address and wait for the ACK or NACK with the last strobe. Then the counter is increased to the new address. As I said, it works fine with I/O chips.

    Thanks
    Josh

    One step further and the last LCD:
    I checked the voltages: supply voltage 3.3volt. used 1uF capacitors for the boost, pin 1 (RST) to plus
    With no SDA or SCL attached to the LCD it reads 1.38 volts. If I attach a 1k resistor to plus, the voltage is almost the same. During Idle time it is suppose to stay high

    What is wrong here?

    Is the pinout on the data sheet wrong? left to right = 1 to 8?

    Can somebody help me, please?

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  • perky

    According to the ST7032 spec the SDA and SCL lines are on DB7 and DB6 respectively. These have a Vol spec of 0.8V with Iol of 1mA (quoted at 25deg C), so that's an equivalent resistance of 3k3 at 3.3V. Generally I2C works well with 4k7 to 10k, so I'd probably use 10k here for some margin, in theory that should get down to less than 0.4V. A 1k5 ohm resistance is too low to get a low enough Vol.

    Mark.

    Edit: OK, I see a problem. You're final SCL clock looks way too short, is this a software I2C master interface you're using? Can you change the pull-up resistors to 10k, and give a proper length SCL pulse at the end? Sampling closer to the rising edge of SCL might help, it shouldn't be changing the SDA state while the clock is high though.

    Edit2: There are small spikes on the SDA at the point where SCL changes. As SDA is open colector and pulled up by a resistor that suggests some noice on Vcc. If the device has feedback internally on SDA, and a too low value of resistor is used meaning the logic low is a little close to the edge, and there's Vcc noise, it's possible that the logic inside the controller lets go of SDA prematurely. So by putting a high value of resistor in you've pulled the signal down, meaning it can tolerate more Vcc noise. At the 50k limit it appears to work, Vcc noise is not enough to trigger a release. I would look carefully then at Vcc, put some decoupling caps close to the module and try to get rid of those little spikes. A combination of using 10k resistors and decent Vcc decoupling may be the solution.

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