Carrier PCB NHD-3.12-25664 has bad layout

cinderblock

• October 11, 2021 20:16

Ignoring the obvious things like basic labelling of IO pins, there are technical flaws with how the board is designed, according to the datasheet:

1. the VDD should not be externally powered by above 2.6V but that is what is brought out and it's common to connect that pin to 3.3V. It still works, but is outside the specified operating conditions.
2. VDDIO and VCI are left floating (but connected to bypass caps)
3. VLSS should be connected to VSS

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  Ted M.

  NHD Staff

  • October 15, 2021 14:17

  Hi Cinderblock,
  
  Thanks for the feedback. We are looking into updating this PCB design and will take these observations into consideration with the new layout.
  
  Regards,

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