NV3035C Dot Clock Lower Timing 6.1MHz

markgm

• August 09, 2016 09:07

Hello,

I am using the NHD-3.5-320240MF-ATXL#-T-1 with a built in NV3035C. I was wondering what the limit is for the 6.1MHz min Dot Clk. Is this related to the retention of the signal level for each TFT cell? The reason I ask is that I have been able to operate it way outside its limits, down to around 1MHz Dot Clk without problems. Obviously when I pause while debugging the screen will fade but this takes a few seconds.

So the question is, since it looks like it is edge driven from the Dot Clk, HSync and VSync, why would it be critical to drive it at 6.1MHz and above? I could understand the upper limit of 8MHz (possibly not achieving the correct levels).

Thanks in advance for any assistance given.

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  Saurabh_B

  • August 09, 2016 11:07

  Writing to the display slower won't necessarily cause problems, however filling the entire display will take longer.
  This can also lead to some flickering of pixels which tend to fall first.

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  markgm

  • August 10, 2016 11:07

  Thanks for the reply. Yes I have seen flickering. I guess the device is based around 60Hz refresh for a 320*240 display hence the 6.4MHz nominal.

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  RandyLee

  • June 05, 2017 11:07

  I've clocked this at 30MHz here (accidentally) and besides the streaks on the screen, I'm getting a nice stable display.  Surprised this runs at all, but I'll take it.
  
  Clocking this at 7.4MHz, I get noticeable flicker.
  
  According to the docs on this, the NV3035C is supposed to come up in "reasonable" settings for this so I haven't done any init code in it, just reset and allow it to do it's thing.
  
  I'm thinking that this should be a nice stable display at this rate and with those default settings.  Maybe this should be set to something else?

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  RandyLee

  • June 05, 2017 13:07

  Found my main problem here: PWM of the backlight.  Had that at 120Hz.  Changed it to 800Hz and this is showing steady now.

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