Image Alignment - 480x272 image on 800x480 TFT

mike_s

Hi Everyone,

I'm just getting through some initial debugging on my board using an STM32H7, connected to the :  NHD-5.0-800480TF-ATXL-CTP
(800x480 TFT)

I'm using the STM32H7 built-in LTDC display controller... STM has sample code/etc for testing out the LCD screen, etc..

so their eval setup used a 480x272 LCD display, whereas I'm using this one above, 800x480..

so after setting up the params correctly, I can display their test image, but I would have expected for the image to have started at the left-side origin, but there is some blank space...

What I'm wondering is if this could happen from an I/O being wrong or shorted?  or would I see scrambled data if that was the case?

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Comments

9 comments

Date Votes
  • Ted M.
    NHD Staff

    Hi Mike,

    I have sent you an email with a recommendation to compare the RGB timings in the example code you're using with the RGB timing values in our 5" TFT's datasheet as a starting point.
    Let us know if this resolves the issue.

    Best Regards,

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  • bricharditede

    i like this, but i would like that image would be a thumbnail that enlarge with a click, and all thumbnail with the same width and large. Is this possible?

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  • mike_s

    Hi All,

    Just wanted to update, that this issue can now be CLOSED as SOLVED.

    The offset shown in that image was because the datasheet in 2018 for this TFT had the  HBP (Horizontal Back Porch) value as 88 pixel clocks, which through trial and error testing I found out was waaayyy too high.  I turned out the HBP needed to be in the 40s area.

    Looks like the datasheet has been updated recently, and it's showing correct values now for HBP as well as better timings for the other values.


    So this TFT is indeed working awesome now, no issues whatsoever!

    Thanks so much,


    - Mike

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  • v8dave

    The offset shown in that image was because the datasheet in 2018 for this TFT had the  HBP (Horizontal Back Porch) value as 88 pixel clocks, which through trial and error testing I found out was waaayyy too high.  I turned out the HBP needed to be in the 40s area.

    This is interesting to know. I have a 7.0" with 800x480 and in the timing, it has HBP also as 88 clocks. I got some timing from Newhaven tech that sets the HBP to 40. I have tried this and the display is much better but I still get tearing and some artifacts on the display. Can I ask what other timing values you used for your 5.0" display? I think the 5 and 7 are the same except for the clock which is latched on the positive edges on the 5.0"

    Cheers
    Dave...

     

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  • mike_s

    Hi Dave,

    I don't have my code in front of me at the moment, but I remember checking the other day against the latest datasheet, and my timing numbers now match exactly what is in the sheet, so I didn't have to tweak anything else...

    Although, I DO encounter similar problems if I push the pixel clock closer to their recommended values of 30-50Mhz...  now it could very well be my board layout, since I didn't do any meandering for the bus lines...I do have series termination, as I originally saw a good bit of reflection on the scope... they are much cleaner now..

    So, I am currently running my pixel clock at 24Mhz, which is 100% clean with no tearing or artifacts... if I push it to 30Mhz and up, things start to go bad...

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  • v8dave

    Thanks Mike

    I suspect I have reflection issues as I didn't install any series termination resistors in the lines. I am considering restringing the PCB to add these to the PCB layout but on the prototype, I will try to install these in the clock and the sync as a minimum. I never had to do this with the previous 7" LCD but it does look like I need to do this on this one.

    PS. I read up on it and there is no need for meandering on the LCD lines as the clocks are not that fast to need this. A good layout is needed though and in my case, I kept the clock clear of the other lines as I saw issues with this before.

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  • v8dave

    I was able to add 22R resistors to the CLK, HSYNC, VSYNC and DEN and reduced the drive current on the RGB lines and now I seem to have a more stable display although I do see some horizontal shift when I use anything but black on the left side of the LCD, but it is looking closer now to being a working LCD.

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  • mike_s

    Hi Dave,

    that's good, I was going to suggest (if by chance you are using an STM32 or similar where you can change the I/O drive strength), to set the I/O 'strength', or in STM32 case, the 'speed', as this made a BIG difference in the I/O signals and reflections...

    I think I have mine set at 'HIGH', which seemed the best (ie VERY HIGH is more in the ballpark of 100mhz or more like SDRAM, etc)

    Also, play with your pixel clock and see if slowing it down a bit cleans up your picture too... as I was saying, I am good at 24Mhz, if I go to 30Mhz or higher, I get distortion, even with all the I/O cleanup I have, it's still not good.. so for now 24mhz is fine for my setup..


    but I could probably figure it out if I scope'd it up again and did more resistance tweaking, but for now I'm ok with where it's at, I have 68R series resistors on my lines, I did all lines with my last board spin..

    - Mike

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  • v8dave

    Thanks, Mike,

    I am running with a Samsung S5P6818 8 core A53 processor board from FriendlyArm (NanoPC T3 Plus)

    I'll try lowering the pixel clock too. Right now it is at 30Mhz. I have the drive level set at 2 for all timing and 1 for the RGB. Values are 0 to 3 for the driver current. I could try 3 and see what it looks like.

    My other post shows what I am seeing now and apart from this, the display looks good otherwise

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