NHD-2.7-12864WDY3 and SSD1322 Spec Sheet Errors (?)
The timing waveforms for the E and /CS signals make no sense as they are drawn and disagree with the logic states listed in the table. The E signal's falling edge is shown as occurring after valid data for read and for write, and the /CS signal is shown changing state from low to high during valid data.
These timings would be closer to correct if both waveforms would be inverted and if the signal identities are exchanged. Can someone confirm this or explain to me how I am misinterpreting the waveforms? These waveforms are reproduced from the SSD1322 Rev 1.2 spec sheet, and it seems as if every OLED manufacturer who is using the SSD1322 in a display has copied the same set of waveforms for use in its spec sheets.
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Hi ChuckR,
The enable pin (E) is latch (High-to-Low) to clock in the bit transfer while the /CS is low. When /CS is LOW it activates the peripheral and when done is brought HIGH. In this case it is perfectly acceptable to GND the line to keep the peripheral active.
Example Command & Data sequence:void Command(unsigned char c){
digitalWrite(CS, LOW);
digitalWrite(DC, LOW);
PORTD = c;
digitalWrite(RW, LOW);
digitalWrite(E, HIGH);
digitalWrite(E, LOW);
digitalWrite(CS, HIGH); //Can be kept LOW by GND
}
void Data(unsigned char c){
digitalWrite(CS, LOW);
digitalWrite(DC, HIGH);
PORTD = d;
digitalWrite(RW, LOW);
digitalWrite(E, HIGH);
digitalWrite(E, LOW);
digitalWrite(CS, HIGH); //Can be kept LOW by GND
}0 -
Zach_P - thanks for your prompt reply. My question about the timing diagram on page 10 is that it does not reflect the signal sequence you describe. The timing diagram shows E transitioning high-to-low when /CS is high. Furthermore the high-to-low transition of E occurs after the interval when the Write data valid interval occurs. The timing diagram shows the following:
void Data(unsigned char c){
digitalWrite(DC,HIGH); //R/W is tied low
digitalWrite(E, HIGH);
digitalWrite(CS, LOW);
PORTD = d;
digitalWrite(CS, HIGH);
digitalWrite(E, LOW);
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@ChuckR Thanks for this Question! Been a year, but info about 6800 mode is still wrong everywhere.
Except, that is, for the timing diagram you mentioned above. That looks to be correct.
I've been trying for hours to get 6800 mode to work with no luck until finding this post.
Had 8080, 4-wire SPI, and 3-wire SPI working fine, but weird results with 6800 mode. Sorta doing something, but not right.
Seems that CS rising is what really latches the data, despite all the literature saying that E does that.
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Hi Ray,
If you keep the CS pin low, you should be able to latch the data with the signal E. We will be updating our website code to reflect this.
We are checking with Solomon if they have an updated version of the datasheet that shows the correct timing diagram.
In the meantime, please let us know if you have any other questions.
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