NHD-21-480480AF-ASXP MIPI DSI Interface

Abeer Ul Haq

• September 13, 2025 09:21

Hi,

I am working with the NHD-21-480480AF-ASXP on an STM32L4R9 and have successfully interfaced it using a single-lane MIPI DSI. I am trying to fill a portion of the LCD with a single color, but the area being filled is larger than expected.

My current timing settings are:

• Horizontal: H_FP = 360, H_BP = 88, H_SYNC = 128

• Vertical: V_FP = 12, V_BP = 32, V_SYNC = 1

• LTDC (Pixel Clock) = 20MHz
• DSI Byte Lane Clock = 40MHz

Could you please advise if these timing parameters are correct, or if there might be a misconfiguration causing this behavior?

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  Engineering Support

  Community moderator

  • September 17, 2025 20:36

  Hi Abeer,

  The following are the recommended timing values for the NHD-2.1-480480AF-ASXP display when using the MIPI interface:

  • HSYNC: 20
  • VSYNC: 6
  • HBP: 60
  • HFP: 40
  • VBP: 10
  • VFP: 10
  • Pixel Clock: 18.2M
  • DSI Byte Lane Clock:  234Mhz

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  Abeer Ul Haq

  • September 18, 2025 13:51

  Can you confirm whether the value you provided is for the Byte Lane Clock or the DSI PHY Clock?
  The calculation does not seem to add up to that number.

  • Total Height = 20 + 60 + 40 + 480 = 600

  • Total Width = 6 + 10 + 10 + 480 = 506

  Pixel Clock = 600 × 506 × 60 = 18.216 MHz
  DSI Byte Lane Clock = Pixel Clock × Color Depth = 18.216 MHz × 16 bpp = 291.456 MHz
  DSI PHY Clock = Pixel Clock × Bytes per Pixel = 18.216 MHz × 2 = 36.432 MHz

  I tested these values and also tried using your DSI Byte Lane Clock as the PHY Clock, since my controller’s maximum settings are:

  • DSI Byte Lane Clock (max) = 62.5 MHz

  • DSI PHY Clock (max) = 500 MHz

  The output remained the same as before.

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  Engineering Support

  Community moderator

  • September 22, 2025 17:43

  Hi Abeer,

  Thank you for your detailed calculations. To clarify, the value I provided is for the Byte Lane Clock. Your calculated value is the correct number when using a 16bpp color depth.

   

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  Abeer Ul Haq

  • September 23, 2025 07:46

  Sorry I swapped the naming. It should be 
  DSI PHY Clock= Pixel Clock × Color Depth = 18.216 MHz × 16 bpp = 291.456 MHz
  DSI Byte Lane Clock = Pixel Clock × Bytes per Pixel = 18.216 MHz × 2 = 36.432 MHz
  
  Let me know if this is correct. 

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  Engineering Support

  Community moderator

  • September 23, 2025 14:31

  Hi Abeer,

  Thank you for the clarification. Yes, your updated calculations look correct.

  Pixel Clock: 18.216 MHz

  DSI Byte Lane Clock: 36.432 MHz

  DSI PHY Clock (Bit Clock): 291.456 MHz

   

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