NHD-3.5-640480EF-MSXP FL7703NI Linux driver

Comments

4 comments

  • Engineering Support
    Community moderator

    Hi Dylan,

    Unfortunately we do not have any linux drivers for this display. However, the Sitronix ST7703 driver IC is similar and may have additional resources available.

    Additionally, please refer to our initialization example code below.

     

    GP_COMMAD_PA(4);W_D(0xB9); /// Set EXTC
    W_D(0xF1);   //1
    W_D(0x12);   //2
    W_D(0x87);   //3

    GP_COMMAD_PA(4);W_D(0xB2); ///Set RSO
    W_D(0x78);      //1 1024Gate(480+136*4+0)
    W_D(0x14);      //2 600RGB
    W_D(0x70);      //3

    GP_COMMAD_PA(11);W_D(0xB3); /// SET RGB
    W_D(0x10);   //1 VBP_RGB_GEN
    W_D(0x10);   //2 VFP_RGB_GEN
    W_D(0x28);   //3 DE_BP_RGB_GEN
    W_D(0x28);   //4 DE_FP_RGB_GEN
    W_D(0x03);   //5
    W_D(0xFF);   //6
    W_D(0x00);   //7
    W_D(0x00);   //8
    W_D(0x00);   //9
    W_D(0x00);   //10

    GP_COMMAD_PA(2);W_D(0xB4); // Set Panel Inversion
    W_D(0x80);   //1 //Zig-zag inversion type D

    GP_COMMAD_PA(3);W_D(0xB5); /// Set BGP
    W_D(0x0A);   //1 vref 
    W_D(0x0A);   //2 nvref

    GP_COMMAD_PA(3);W_D(0xB6); /// Set VCOM
    W_D(0x70);   //1 F_VCOM 
    W_D(0x70);   //2 B_VCOM  

    GP_COMMAD_PA(2);W_D(0xB8); ///Set ECP
    W_D(0x26);  //0x75 for 3 Power Mode);W_D(0x25 for Power IC Mode  

    GP_COMMAD_PA(28);W_D(0xBA); /// Set DSI
    W_D(0x31);   //1//33:4Lane);W_D(32:3Lane    31:2Lane
    W_D(0x81);   //2
    W_D(0x05);   //3
    W_D(0xF9);   //4
    W_D(0x0E);   //5
    W_D(0x0E);   //6
    W_D(0x20);   //7
    W_D(0x00);   //8
    W_D(0x00);   //9
    W_D(0x00);   //10
    W_D(0x00);   //11
    W_D(0x00);   //12
    W_D(0x00);   //13
    W_D(0x00);   //14
    W_D(0x44);   //15
    W_D(0x25);   //16
    W_D(0x00);   //17
    W_D(0x91);   //18
    W_D(0x0A);   //19
    W_D(0x00);   //20
    W_D(0x00);   //21
    W_D(0x01);   //22
    W_D(0x4F);   //23
    W_D(0x01);   //24
    W_D(0x00);   //25
    W_D(0x00);   //26
    W_D(0x37);   //27

    GP_COMMAD_PA(2);W_D(0xBC); /// Set VDC
    W_D(0x47);   //1

    GP_COMMAD_PA(4);W_D(0xBF); ///Set PCR
    W_D(0x02);  //1
    W_D(0x11);  //2
    W_D(0x00);  //3

    GP_COMMAD_PA(10);W_D(0xC0); /// Set SCR
    W_D(0x73);   //1
    W_D(0x73);   //2
    W_D(0x50);   //3
    W_D(0x50);   //4
    W_D(0x00);   //5 A0
    W_D(0x00);   //6
    W_D(0x12);   //7
    W_D(0x73);   //8
    W_D(0x00);   //9

    GP_COMMAD_PA(18);W_D(0xC1); ///Set POWER
    W_D(0x54);   //1 VBTHS VBTLS     73
    W_D(0x00);
    W_D(0x32);   //3 VSPR
    W_D(0x32);   //4 VSNR
    W_D(0x77);   //5 VSP VSN
    W_D(0xF4);   //6 APS  F1
    W_D(0x77);   //7 VGH3 VG3L
    W_D(0x77);   //8 VGH3 VGL3
    W_D(0xCC);   //9 VGH2 VGL2
    W_D(0xCC);   //10 VGH2 VGL2
    W_D(0xFF);   //11 VGH VGL
    W_D(0xFF);   //12 VGH VGL
    W_D(0x11);   //13
    W_D(0x11);   //14
    W_D(0x00);   //15
    W_D(0x00);   //16
    W_D(0x31);   //17 VSP VSN DET EN  32

    GP_COMMAD_PA(13);W_D(0xC7); //
    W_D(0x10);   //1   enable VOUT output
    W_D(0x00);   //2
    W_D(0x0A);   //3
    W_D(0x00);   //4
    W_D(0x00);   //5
    W_D(0x00);   //6   setting VOUT at 3.3V
    W_D(0x00);   //7   HOUT SEL  D6:D5    VOUT SEL D1:D0
    W_D(0x00);   //8     PWM SEL D1:D0
    W_D(0xED);   //9        D7:MIPI ERR DIS TE/  D6:VGL DET DIS TE/  D5:VGH DET DIS TE/  D4:DBV ZERO DIS TE/  D3:LVPUR DIS TE/  D2:TE ONLY AT NORMAL/  D1:CRC MATC/  D0:REF_CRC DIS TE
    W_D(0xC7);   //10       D7:OLED_CMD/  D6:N_CMD_EN/  D5:HS_STOP_CMD_EN/  D4:MIPI STOP 09 PAR3 EN/  D3:CHECK VSYNC/  D2:MIPI STOP 09 EN/  D1:TE STOP RD EN/  D0:STATE ERR READ EN
    W_D(0x00);   //11
    W_D(0xA5);   //12

    GP_COMMAD_PA(5);W_D(0xC8); /// Set SCR
    W_D(0x10);  //1
    W_D(0x40);  //2
    W_D(0x1E);  //3
    W_D(0x03);  //4

    GP_COMMAD_PA(2);W_D(0xCC); /// Set Panel
    W_D(0x0B);   //1 Forward:0x0B);W_D(Backward:0x07

    GP_COMMAD_PA(35);W_D(0xE0); ///Set Asymmetric gamma2.2
    W_D(0x00);  //1
    W_D(0x05);  //2  04
    W_D(0x09);  //3  07
    W_D(0x29);  //4  28
    W_D(0x3C);  //5
    W_D(0x3F);  //6
    W_D(0x3B);  //7  38
    W_D(0x37);  //8  35
    W_D(0x05);  //9
    W_D(0x0A);  //10
    W_D(0x0C);  //11 0C
    W_D(0x10);  //12 11
    W_D(0x13);  //13
    W_D(0x10);  //14
    W_D(0x13);  //15
    W_D(0x12);  //16
    W_D(0x1A);  //17
    W_D(0x00);  //1
    W_D(0x05);  //2 04
    W_D(0x09);  //3
    W_D(0x29);  //4 28
    W_D(0x3C);  //5
    W_D(0x3F);  //6
    W_D(0x3B);  //7  38
    W_D(0x37);  //8  35
    W_D(0x05);  //9
    W_D(0x0A);  //10
    W_D(0x0C);  //11 0D
    W_D(0x10);  //12 11
    W_D(0x13);  //13
    W_D(0x10);  //14
    W_D(0x13);  //15
    W_D(0x12);  //16 13
    W_D(0x1A);  //17

    GP_COMMAD_PA(8);W_D(0xE1); /// Set
    W_D(0x11);   //1
    W_D(0x11);   //2
    W_D(0x91);   //3
    W_D(0x00);   //4 D7:D5:VGH DET SEL/  D4:D0:VGL DET SEL
    W_D(0x00);   //5 D5:D0:VSN DET SE
    W_D(0x00);   //6 D5:D0:VSP DET SE
    W_D(0x00);   //7 D7:PUREN_IOVCC/  D6:D4:IOVCC PUR_SEL/  D3:D2:DCHG1/  D1:D0:DCHG2

    GP_COMMAD_PA(15);W_D(0xE3); /// Set EQ
    W_D(0x07);   //1  PNOEQ 03                      
    W_D(0x07);   //2  NNOEQ 03                      
    W_D(0x0B);   //3  PEQGND                      
    W_D(0x0B);   //4  NEQGND                      
    W_D(0x03);   //5  PEQVCI  00                    
    W_D(0x0B);   //6  NEQVCI  07                    
    W_D(0x00);   //7  PEQVCI1                     
    W_D(0x00);   //8  NEQVCI1                     
    W_D(0x00);   //9  VCOM_PULLGND_OFF            
    W_D(0x00);   //10 VCOM_PULLGND_OFF            
    W_D(0xFF);   //11 VCOM_IDLE_ON             
    W_D(0x04);   //12 D4:Source blk pre charge/  D3:1X1 PATTERN DET  /D2:TCON USE DGC VS/  D1:D0:OPON DLY    84                  
    W_D(0xC0);   //13 defaut C0 ESD detect function   D5:D4:ESD OPT P/  D3:D2:SD LE/  D1:SDOPBIAS/  D0:TCON HS SYNC SEL
    W_D(0x10);   //14 SLPOTP                      

    GP_COMMAD_PA(64);W_D(0xE9); /// Set GIP
    W_D(0x01);  //1  PANSEL
    W_D(0x00);  //2  SHR_0[11:8]
    W_D(0x0E);  //3  SHR_0[7:0]  08
    W_D(0x00);  //4  SHR_1[11:8]
    W_D(0x00);  //5  SHR_1[7:0] 
    W_D(0xB0);  //6  SPON[7:0]                 
    W_D(0xB1);  //7  SPOFF[7:0]
    W_D(0x11);  //8  SHR0_1[3:0]);W_D( SHR0_2[3:0]
    W_D(0x31);  //9  SHR0_3[3:0]);W_D( SHR1_1[3:0]
    W_D(0x23);  //10 SHR1_2[3:0]);W_D( SHR1_3[3:0]
    W_D(0x28);  //11 SHP[3:0]);W_D( SCP[3:0]
    W_D(0x10);  //12 CHR[7:0]  0A
    W_D(0xB0);  //13 CON[7:0] 
    W_D(0xB1);  //14 COFF[7:0]
    W_D(0x27);  //15 CHP[3:0]);W_D( CCP[3:0]
    W_D(0x08);  //16 USER_GIP_GATE[7:0]           2A
    W_D(0x00);  //17 CGTS_L[21:16] 
    W_D(0x04);  //18 CGTS_L[15:8]    Gout11 STV
    W_D(0x02);  //19 CGTS_L[7:0]                Gout2  STV    
    W_D(0x00);  //20 CGTS_INV_L[21:16] 
    W_D(0x00);  //21 CGTS_INV_L[15:8]
    W_D(0x00);  //22 CGTS_INV_L[7:0]    GOUT5  INV  10
    W_D(0x00);  //23 CGTS_R[21:16]
    W_D(0x04);  //24 CGTS_R[15:8]   Gout11 STV
    W_D(0x02);  //25 CGTS_R[7:0]    Gout2  STV                                               
    W_D(0x00);  //26 CGTS_INV_R[21:16]
    W_D(0x00);  //27 CGTS_INV_R[15:8]
    W_D(0x00);  //28 CGTS_INV_R[7:0]  GOUT5  INV  10
    W_D(0x88);  //29 COS1_L[3:0] );W_D(COS2_L[3:0] );W_D(//  VSTF4U  VSTF2U
    W_D(0x88);  //30 COS3_L[3:0] );W_D(COS4_L[3:0] );W_D(//
    W_D(0xBA);  //31 COS5_L[3:0] );W_D(COS6_L[3:0] );W_D(//  FLCA  FLCB
    W_D(0x60);  //32 COS7_L[3:0] );W_D(COS8_L[3:0] );W_D(//  VCK1  VCK3
    W_D(0x24);  //33 COS9_L[3:0] );W_D(COS10_L[3:0]);W_D(//  VCK5  VCK7
    W_D(0x08);  //34 COS11_L[3:0]);W_D(COS12_L[3:0]);W_D(//  VSTF1D   VSTF3D
    W_D(0x88);  //35 COS13_L[3:0]);W_D(COS14_L[3:0]);W_D(//
    W_D(0x88);  //36 COS15_L[3:0]);W_D(COS16_L[3:0]);W_D(//         
    W_D(0x88);  //37 COS17_L[3:0]);W_D(COS18_L[3:0]);W_D(//  
    W_D(0x88);  //38 COS19_L[3:0]);W_D(COS20_L[3:0]);W_D(//
    W_D(0x88);  //39 COS21_L[3:0]);W_D(COS22_L[3:0]);W_D(//
    W_D(0x88);  //40 COS1_R[3:0] );W_D(COS2_R[3:0] );W_D(//   VSTF3U  VSTF1U
    W_D(0x88);  //41 COS3_R[3:0] );W_D(COS4_R[3:0] );W_D(//
    W_D(0xBA);  //42 COS5_R[3:0] );W_D(COS6_R[3:0] );W_D(//  FLCA  FLCB
    W_D(0x71);  //43 COS7_R[3:0] );W_D(COS8_R[3:0] );W_D(//  VCK2  VCK4
    W_D(0x35);  //44 COS9_R[3:0] );W_D(COS10_R[3:0]);W_D(//  VCK6  VCK8
    W_D(0x18);  //45 COS11_R[3:0]);W_D(COS12_R[3:0]);W_D(//  VSTT2D VSTF4D
    W_D(0x88);  //46 COS13_R[3:0]);W_D(COS14_R[3:0]);W_D(//
    W_D(0x88);  //47 COS15_R[3:0]);W_D(COS16_R[3:0]);W_D(//
    W_D(0x88);  //48 COS17_R[3:0]);W_D(COS18_R[3:0]);W_D(//
    W_D(0x88);  //49 COS19_R[3:0]);W_D(COS20_R[3:0]);W_D(//
    W_D(0x88);  //50 COS21_R[3:0]);W_D(COS22_R[3:0]);W_D(//
    W_D(0x00);  //51 TCONOPTION
    W_D(0x00);  //52 OPTION
    W_D(0x00);  //53 OTPION
    W_D(0x01);  //54 OPTION
    W_D(0x00);  //55 CHR2
    W_D(0x00);  //56 CON2
    W_D(0x00);  //57 COFF2
    W_D(0x00);  //58 CHP2);W_D(CCP2
    W_D(0x00);  //59 CKS 22 21 20 19 18 17
    W_D(0x00);  //60 CKS 16 15 14 13 12 11 10 9
    W_D(0x00);  //61 CKS 8 7 6 5 4 3 2 1                                                 
    W_D(0x00);  //62 COFF[7:6]   CON[5:4]    SPOFF[3:2]    SPON[1:0]
    W_D(0x00);  //63 COFF2[7:6]  CON2[5:4]


    GP_COMMAD_PA(62);W_D(0xEA); /// Set GIP2
    W_D(0x97);  //1  ys2_sel[1:0]
    W_D(0x0A);  //2  user_gip_gate1[7:0]
    W_D(0x82);  //3  ck_all_on_width1[5:0]
    W_D(0x02);  //4  ck_all_on_width2[5:0]
    W_D(0x03);  //5  ck_all_on_width3[5:0]
    W_D(0x07);  //6  ys_flag_period[7:0]
    W_D(0x00);  //7  ys_2
    W_D(0x00);  //8  user_gip_gate1_2[7:0]
    W_D(0x00);  //9  ck_all_on_width1_2[5:0]
    W_D(0x00);  //10 ck_all_on_width2_2[5:0]
    W_D(0x00);  //11 ck_all_on_width3_2[5:0]
    W_D(0x00);  //12 ys_flag_period_2[7:0]
    W_D(0x81);  //13 COS1_L[3:0] );W_D(COS2_L[3:0] );W_D(//     VSTF4U  VSTF2U                                 
    W_D(0x88);  //14 COS3_L[3:0] );W_D(COS4_L[3:0] );W_D(//  
    W_D(0xBA);  //15 COS5_L[3:0] );W_D(COS6_L[3:0] );W_D(//     FLCA FLCB
    W_D(0x17);  //16 COS7_L[3:0] );W_D(COS8_L[3:0] );W_D(//     VCK1 VCK3    
    W_D(0x53);  //17 COS9_L[3:0] );W_D(COS10_L[3:0]);W_D(//     VCK5 VCL7
    W_D(0x88);  //18 COS11_L[3:0]);W_D(COS12_L[3:0]);W_D(// 
    W_D(0x88);  //19 COS13_L[3:0]);W_D(COS14_L[3:0]);W_D(//
    W_D(0x88);  //20 COS15_L[3:0]);W_D(COS16_L[3:0]);W_D(//         
    W_D(0x88);  //21 COS17_L[3:0]);W_D(COS18_L[3:0]);W_D(//  
    W_D(0x88);  //22 COS19_L[3:0]);W_D(COS20_L[3:0]);W_D(//
    W_D(0x88);  //23 COS21_L[3:0]);W_D(COS22_L[3:0]);W_D(//
    W_D(0x80);  //24 COS1_R[3:0] );W_D(COS2_R[3:0] );W_D(//     VSTF3U  VSTF1U
    W_D(0x88);  //25 COS3_R[3:0] );W_D(COS4_R[3:0] );W_D(//                        
    W_D(0xBA);  //26 COS5_R[3:0] );W_D(COS6_R[3:0] );W_D(//      FLCA FLCB 
    W_D(0x06);  //27 COS7_R[3:0] );W_D(COS8_R[3:0] );W_D(//      VCK2 VCK4
    W_D(0x42);  //28 COS9_R[3:0] );W_D(COS10_R[3:0]);W_D(//      VCK6 VCK8
    W_D(0x88);  //29 COS11_R[3:0]);W_D(COS12_R[3:0]);W_D(//
    W_D(0x88);  //30 COS13_R[3:0]);W_D(COS14_R[3:0]);W_D(//
    W_D(0x88);  //31 COS15_R[3:0]);W_D(COS16_R[3:0]);W_D(//
    W_D(0x88);  //32 COS17_R[3:0]);W_D(COS18_R[3:0]);W_D(//
    W_D(0x88);  //33 COS19_R[3:0]);W_D(COS20_R[3:0]);W_D(//
    W_D(0x88);  //34 COS21_R[3:0]);W_D(COS22_R[3:0]);W_D(
    W_D(0x23);  //35 EQOPT );W_D( EQ_SEL
    W_D(0x00);  //36 EQ_DELAY[7:0]                                    
    W_D(0x00);  //37 EQ_DELAY_HSYNC [3:0]
    W_D(0x02);  //38 HSYNC_TO_CL1_CNT9[8]
    W_D(0x80);  //39 HSYNC_TO_CL1_CNT9[7:0]        
    W_D(0x00);  //40 HIZ_L
    W_D(0x00);  //41 HIZ_R
    W_D(0x00);  //42 CKS_GS[21:16]
    W_D(0x00);  //43 CKS_GS[15:8]
    W_D(0x00);  //44 CKS_GS[7:0]
    W_D(0x00);  //45 CK_MSB_EN[21:16]
    W_D(0x00);  //46 CK_MSB_EN[15:8]
    W_D(0x00);  //47 CK_MSB_EN[7:0] 
    W_D(0x00);  //48 CK_MSB_EN_GS[21:16]
    W_D(0x00);  //49 CK_MSB_EN_GS[15:8]
    W_D(0x00);  //50 CK_MSB_EN_GS[7:0] 
    W_D(0x00);  //51  SHR2[11:8]
    W_D(0x00);  //52  SHR2[7:0]
    W_D(0x00);  //53  SHR2_1[3:0] SHR2_2
    W_D(0x00);  //54  SHR2_3[3:0]
    W_D(0x00);  //55 SHP1[3:0]);W_D(x
    W_D(0x00);  //56 SPON1[7:0]
    W_D(0x00);  //57 SPOFF1[7:0]
    W_D(0x00);  //58 SHP2[3:0]
    W_D(0x00);  //59 SPON2[7:0]
    W_D(0x00);  //60 SPOFF2[7:0]
    W_D(0x00);  //61 SPOFF2[9:8]/SPON2[9:8]/SPOFF1[9:8]/SPON1[9:8]

    GP_COMMAD_PA(4);W_D(0xEF); //
    W_D(0xFF);  //1 
    W_D(0xFF);  //2    
    W_D(0x01);  //3 

    GP_COMMAD_PA(1);W_D(0x11); //Sleep Out
    delay_ms(250);     //150

    GP_COMMAD_PA(1);W_D(0x29); //Display On
    delay_ms(50);

     

    0
  • Dylan Zheng

    thanks

    0
  • Dylan Zheng

    Dear Sir/Madam,

     

    I check the datasheet of FL7703, there is no register 0xE1.

    I am wondering if this is a typo?

    0
  • Engineering Support
    Community moderator

    Hi Dylan,

    This initialization sample code is ported from another device, so any functions that do not pertain to the registers defined in the FL7703 can be ignored or removed.

    0

Please sign in to leave a comment.