NHD-2.7-12864WDY3 and SSD1322 Spec Sheet Errors (?)

Comments

2 comments

  • Zach P
    NHD Staff

    Hi ChuckR,

    The enable pin (E) is latch (High-to-Low) to clock in the bit transfer while the /CS is low. When /CS is LOW it activates the peripheral and when done is brought HIGH. In this case it is perfectly acceptable to GND the line to keep the peripheral active.

    Example Command & Data sequence:

    void Command(unsigned char c){
       digitalWrite(CS, LOW);               
       digitalWrite(DC, LOW);
       PORTD = c;
       digitalWrite(RW, LOW);
       digitalWrite(E, HIGH);
       digitalWrite(E, LOW);
       digitalWrite(CS, HIGH); //Can be kept LOW by GND
    }

    void Data(unsigned char c){
       digitalWrite(CS, LOW);               
       digitalWrite(DC, HIGH);
       PORTD = d;
       digitalWrite(RW, LOW);
       digitalWrite(E, HIGH);
       digitalWrite(E, LOW);
       digitalWrite(CS, HIGH); //Can be kept LOW by GND
    }
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  • ChuckR

    Zach_P - thanks for your prompt reply. My question about the timing diagram on page 10 is that it does not reflect the signal sequence you describe. The timing diagram shows E transitioning high-to-low when /CS is high. Furthermore the high-to-low transition of E occurs after the interval when the Write data valid interval occurs. The timing diagram shows the following:

    void Data(unsigned char c){
       digitalWrite(DC,HIGH);  //R/W is tied low
       digitalWrite(E, HIGH);               
       digitalWrite(CS, LOW);
       PORTD = d;
       digitalWrite(CS, HIGH);
       digitalWrite(E, LOW);
    }
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