NHD-2.7-12864WDY3 and SSD1322 Spec Sheet Errors (?)
I am just beginning to use the NHD-2.7-12864WDY3 display, and initially I'm connecting it in the 8-bit parallel 6800 mode. On page 10 of the Newhaven spec sheet, there's a table showing the logic states of E, R/W, /CS and D/C, and at the bottom of the page is a timing diagram showing the relationships of these signals per the chart of timings immediately above it.
The timing waveforms for the E and /CS signals make no sense as they are drawn and disagree with the logic states listed in the table. The E signal's falling edge is shown as occurring after valid data for read and for write, and the /CS signal is shown changing state from low to high during valid data.
These timings would be closer to correct if both waveforms would be inverted and if the signal identities are exchanged. Can someone confirm this or explain to me how I am misinterpreting the waveforms? These waveforms are reproduced from the SSD1322 Rev 1.2 spec sheet, and it seems as if every OLED manufacturer who is using the SSD1322 in a display has copied the same set of waveforms for use in its spec sheets.
The timing waveforms for the E and /CS signals make no sense as they are drawn and disagree with the logic states listed in the table. The E signal's falling edge is shown as occurring after valid data for read and for write, and the /CS signal is shown changing state from low to high during valid data.
These timings would be closer to correct if both waveforms would be inverted and if the signal identities are exchanged. Can someone confirm this or explain to me how I am misinterpreting the waveforms? These waveforms are reproduced from the SSD1322 Rev 1.2 spec sheet, and it seems as if every OLED manufacturer who is using the SSD1322 in a display has copied the same set of waveforms for use in its spec sheets.
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Hi ChuckR,
The enable pin (E) is latch (High-to-Low) to clock in the bit transfer while the /CS is low. When /CS is LOW it activates the peripheral and when done is brought HIGH. In this case it is perfectly acceptable to GND the line to keep the peripheral active.
Example Command & Data sequence:void Command(unsigned char c){
digitalWrite(CS, LOW);
digitalWrite(DC, LOW);
PORTD = c;
digitalWrite(RW, LOW);
digitalWrite(E, HIGH);
digitalWrite(E, LOW);
digitalWrite(CS, HIGH); //Can be kept LOW by GND
}
void Data(unsigned char c){
digitalWrite(CS, LOW);
digitalWrite(DC, HIGH);
PORTD = d;
digitalWrite(RW, LOW);
digitalWrite(E, HIGH);
digitalWrite(E, LOW);
digitalWrite(CS, HIGH); //Can be kept LOW by GND
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Zach_P - thanks for your prompt reply. My question about the timing diagram on page 10 is that it does not reflect the signal sequence you describe. The timing diagram shows E transitioning high-to-low when /CS is high. Furthermore the high-to-low transition of E occurs after the interval when the Write data valid interval occurs. The timing diagram shows the following:
void Data(unsigned char c){
digitalWrite(DC,HIGH); //R/W is tied low
digitalWrite(E, HIGH);
digitalWrite(CS, LOW);
PORTD = d;
digitalWrite(CS, HIGH);
digitalWrite(E, LOW);
}0
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