NHD-7.0-800480EF-ASXN - No Graphics

Comments

5 comments

  • Ted M.
    NHD Staff

    Hi RAGHUL,

    It's possible the voltage levels for the display's 24-bit RGB data and control lines are also borderline.
    The logic levels for a high must be at least 0.7V*VDD or > 2.31V with a 3.3V supply.
    The logic levels for a low must be equal or lower than 0.3V*VDD or < 0.99V with a 3.3V supply.
    Are the logic lines from the SoM able to source enough current to drive the 24-bit RGB data and control lines?

    Regards,

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  • RAGHUL

    Thanks for your quick reply.
    The RGB lines are at 3.3V for logic high and 0V for logic low. Moreover the display was working fine for two days.
    Our main concern is about the PCLK signal. Whether it is supposed to be like that, as shown in the attached image.

    Thank You for your time.

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  • Ted M.
    NHD Staff

    Hi RAGHUL,

    Please clarify if you are measuring the DCLK signal input at pin 30 of this display or somewhere else.

    Regards,

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  • RAGHUL

    Yes. It is the 30th pin. And I'm measuring exactly at the end of the display cable.

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  • Ted M.
    NHD Staff
    Hi RAGHUL,

    Please check the DCLK frequency as it should be a minimum of 28.2MHz up to 40MHz max.
    The voltage for the DCLK signal is also too low.  Is it possible there are losses in the line driving the display?
    If the clock source from the MCU cannot supply enough current, it could explain the voltage drop measured with the display connected.

    Regards,
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